Search-lock system

ABSTRACT

A received RF signal is mixed with the output of a voltagecontrolled local oscillator to provide an IF signal which is simultaneously passed to a frequency discriminator and a circulating memory. Control voltage for the oscillator is provided by an AFC unit which comprises an integrator receiving selected constant voltage inputs. During the search mode a search ramp is generated by the integrator. A flyback circuit causes the search voltage to repeat its traverse over a prescribed range. Bipolar video discriminator outputs above a predetermined threshold place the system in the lock mode and selectively gate two settable, constant voltage inputs to furnish a triangle wave integrator output centered on a voltage corresponding to the desired local oscillator frequency. The oscillator output is mixed with the stored IF to produce a replica of the input signal.

United States Patent [15] 3,675,132 Hansen et al. 1 July 4, 1972 [541SEARCH-LOCK SYSTEM 3,569,838 311971 Blair .325/423 LF. MEMORY [72]inventors: Neil W. Hansen, Pompton Plains, N..l.;

N m Primary Examiner-Albert J. Mayer an ommn' New York N YAttorney-Richard S. Sciascia and Henry Hansen [73] Assignee: The UnitedStates ul America as represented by the Secretary of the Navy [57]ABSTRACT Filedi I- 31, 1970 A received RF signal is mixed with theoutput of a voltage- [21] Appl.No.: 68,581 controlled local oscillatorto provide an lF signal which is slmultaneously passed to a frequencydiscnminator and a euculating memory. Control voltage for the oscillatoris provided .8- CL R, an uni! comprises an intcg at cceiving 328/73,329/122, 329/145, 33l/4, 33l/l0, 331/14, selected constant voltageinputs. During the search mode a 33Un' 331/32 search ramp is generatedby the integrator A llyhuck circuit [5]] lllll. Cl. .JlMb 1/26 causesthe sfinch vohage to "spam its "averse vol. a [58] Fltld 0f SQII'CII..325/346,.4\6423', pescribed rangc' P video discriminator outputs abovea 4 33 122 E55 f ia gg predetermined threshold place the system in thelock mode I i h i and selectively gate two settable, constant voltageinputs to furnish a trian le wave inte rator output centered on avoltage (1' thd' dl 1 Mt f Th correspon mg to e esire oca osci a orrequency. e [56] Cm oscillator output is mixed with the stored [F toproduce a UNITED STATES PATENTS replica of the input signal- 2,789,2264/l957 Nibbe ..33l/4 8 Claims, 6 Drawing Figures REPl-ICJ RE OUTPUT "LLUP MIXER RECEIVED RF INPUV l0 l 12w DOWN mm 5373?;

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lllllll a l l l I I I lllllllllll'llllln lllll l i I l I I i llSEARCH-LOCK SYSTEM STATEMENT OF GOVERNMENT INTEREST The inventiondescribed herein may be manufactured and used by or for the Governmentof the United States of America for governmental purposes without thepayment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION The invention relates in general to radarreceivers and more particularly to search-lock systems for radarreceivers employing automatic frequency control of a local oscillator.

The conventional radar receiver is essentially a special type ofsuperheterodyne receiver. Its function is to receive weak echoesreturned to the antenna system by a target, combine them in a crystalmixer with the RF signals from a local oscillator, amplify the resultantIF or difference signal, detect the pulse envelope, amplify theresulting DC pulses and feed them to the radar indicator. In order tokeep radar receivers in tune with their companion transmitters, somemeans of automatic frequency control of the local oscillator frequencyis commonly used, especially in high frequency, microwave radar. A smallfraction of the RF energy from the transmitter line is mixed with aportion of the RF energy from the local oscillator. The resultant IFfrequency representing the difl'erence between transmitter RF and localoscillator RF is amplified, rectified and applied via control circuitsto tune the local oscillator frequency. If the IF is of the correctfrequency, the local oscillator frequency is held constant. If the IF istoo low or too high, voltage is applied to the local oscillator causingthe frequency to shifl accordingly. A frequency discriminator circuitproducing a bipolar video output is commonly employed to test thefrequency of the IF signal.

In adjusting the local oscillator frequency, two distinct types ofautomatic frequency control have been used in prior radar receivers.Proportional AFC generally applies corrective voltages which areproportional to the magnitude of the error indicated by thediscriminator video output. These voltages are applied directly to thelocal oscillator frequency control circuit to cause the frequency tochange in a direction to minimize the IF frequency error. A second typeof AFC, termed the bang-bang method, applies a fixed corrective voltagein one direction to repeatedly correct the oscillator frequency. If theIF frequency passes through the discriminator center or cross-overfrequency and the video output exceeds a voltage threshold, thebang-bang AFC generates a type of flyback signal, whose magnitude isindependent of the specific discriminator output, to rapidly return theoscillator frequency to a corresponding level on the other side of thecenter frequency so that the time-averaged discriminator output voltageis zero.

In certain situations it is desirable to provide a radar receiver whichis not continuously tuned to a nominally constant transmitter frequency,but rather sweeps a prescribed bandwidth to search for received radarpulses whose exact frequency is not predictable. This type of receiveris nonnally designed to produce an output signal which duplicates thedetected radar pulses. Once the receiver has locked on to radar pulsesof a given carrier frequency, it must follow or track any subsequentchange in the received frequency. In an environment of random noisespikes and pulsed radars with anomalous pulse repetition frequencies(P.R.F.) and varying frequency signals, search-lock receiver systemsemploying either the pure proportional or the pure bang-bang system havebeen found to be inadequately responsive. In the bangbang system, if thelocal oscillator executes a linear frequency sweep during search mode, arapid correction indicating the IF center frequency has been passed isfollowed by resumption of the frequency sweep at the same slope as inthe search mode. Low P.R.F. signals may occur infrequently enough toallow the system to sweep out of the passband during the interpulseperiod. Too slow a search rate, on the other hand, will result inseveral pulses occurring within the pamband before control can beaccomplished, rendering the system incapable of following RF signalsdrifting in the same direction as the search ramp. Moreover, upon lossof the correction signal the local oscillator would go into the searchmode, no frequency memory mechanism being present in the bang-bangsystem.

The proportional system also has drawbacks in the searchlock receiversince its accuracy depends on the amount of input information.Proportional AFC may require several pulses to accurately lock on to areceived signal. With proportional AFC the oscillator will go from thesearch mode to the lock mode whenever a discriminator output occurs. Thesystem must be externally reset to the search mode. While theproportional SWIG"! has inherent frequency memory, the correction rateis not adjustable in accordance with the P.R.F. or frequency stabilityof received pulses. Moreover, a noise spike may cause the proportionalsystem to incorrectly lock requiring reset whereas the bang-bang systemcannot be halted by an isolated spurious spike.

SUMMARY OF THE INVENTION Accordingly one of the objects of die inventionis to permit an independently controlled rate of correction of the localoscillator frequency in two directions. Another object of the inventionis to render the search-lock system invulnerable to random noise spikes.A further object of the invention is to improve the tracking capabilityof search-lock system by providing frequency memory in a nonproportionalAFC system.

These and other objects of the invention are achieved by mixing anincoming RF signal with the output of the voltage controlled localoscillator to provide an IF signal which is stored in a circulatingmemory. A portion of the IF signal is amplified and to a frequencydiscriminator which produces a bipolar video output if the IF is withina predetermined bandwidth. Control voltage for the oscillator isprovided by an integrator which receives selected constant voltageinputs. During the search mode a rising-voltage search ramp is generatedby the integrator. A flyback circuit causes the search voltage to repeatits traverse over a prescribed range. Bipolar video outputs above apredetermined threshold place the system in the lock mode andselectively gate two corresponding constant voltage sources to furnish atriangle wave integrator output. The oscillator output is mixed with thestored IF to produce an RF output corresponding to the input signal.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a block diagram of thesearch-lock system according to the invention;

FIG. 2 is a block diagram ofan AFC unit ofFIG. 1;

FIG. 3 is a block diagram of a limit detector of FIG. 2;

FIG. 4 is a block diagram of a correction voltage control of FIG. 2;

FIG. 5 is a timing diagram illustrating typical signals in the searchmode; and

FIG. 6 is a timing diagram of typical signals in bod: search and lockmodes.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, asearch-lock system is depicted in which received signals normallycontaining random noise as well as RF radar pulses, are fed to a downmixer 10. A voltage controlled local oscillator 11 supplies a varying RFoutput to a power divider 12 which may comprise a resistive network orwaveguide device depending on the frequency ranges employed. A portionof the RF from local oscillator II is passed by divider 12 to down mixer10 where it is combined with the received RF input to produce an IFsignal representing the difference between the frequencies of the twoinputs to mixer 10. If the received RF input comprises pulsed RF signalshaving a carrier frequency 1;, and the local oscillator signal is acontinuous-wave (CW) RF signal of frequency f the IF output of mixerwill be pulses having the same P.R.F. and pulse width as the received RFwith a carrier frequency of f}, f,. The IF signal is passed via an IFamplifier 13 to a power divider 14 which may comprise a suitableresistive network applying a portion of the amplified [F signal toanother IF amplifier 15 whose output is passed to frequencydiscriminator 16 which may comprise a conventional double-tuned detectorof the type commonly used in radar receivers for distinguishing betweenthose IF signals which are above and below a center or crossoverfrequency. The discriminator has a passband width centered on thecrossover frequency and equal to the sum of the bandwidths of the twotuned circuits. The crossover point is established as that frequency forwhich equal positive and negative voltage outputs from each tunedcircuit occur. Discriminator 16 is further equipped with two equallyspaced positive and negative output threshold levels between which nooutput from discriminator 16 will be present. The output ofdiscriminator 16 is conventionally referred to as a bipolar videooutput. There are two frequency zones for which discriminator 16 willproduce an output. For example, a positive voltage output would indicatethat the frequency was slightly above the center frequency but not outof the bandwidth. In any case, no video output will occur if the IFfrequency is equal to the center frequency. The output of discriminator16 is passed via video amplifier 17 to an automatic frequency controlunit 18 whose output through a voltage amplifier 19 controls thefrequency of local oscillator l l.

A portion of the amplified IF signal is routed by power divider 14 to acirculating memory 21 which may comprise an IF amplifier producing thememory output and having a feedback loop from the output to theamplifier input through a resistance, a switch means and a delay media,connected in series with each other. The delay media may comprise aconventional delay line or an acoustic delay device typicallyintroducing a delay in the range of 0.1 to 0.5 microseconds. The switchmay be a semiconductor diode switch at microwave frequencies or anamplifier operated at cut-off. More sophisticated embodiments ofcirculating memories, sometimes called ring around memory systems,usually include limiter devices to prevent overdrive, filters to limitbandwidth and equalizers to flatten gain characteristics over the entirebandwidth encountered. If a single lF pulse enters circulating memory21, it is amplified and returned to the input through the delay media byclosing the switch. The delayed pulse re-enters the amplifier, isreamplified and passed around again through the delay media to theinput. The continuing process ideally produces a continuous pulsedoutput, each pulse being a replica of the original single RF pulse. Theoutput of memory 21 is passed to up mixer 22 which combines thememorized or stored 1F with a portion of the RF output from localoscillator l l supplied by divider 12 to provide a sum frequencymodulated by the memorized pulse envelope, thus duplicating the receivedRF input carrier frequency.

Referring now to FIG. 2, the bmic components of the AFC unit include anintegrator 26 having four constant voltage inputs only one of which inenergized at any given time. Integrator 26 provides a linearlyincreasing or decreasing output voltage a a function of the constantinput voltage expressed by the following equation:

where It represents a circuit constant; V is the input voltage, in thiscase a constant; and V is the output voltage. In order to maintain anapproximate mathematical integration, it is necessary for the RC timeconstant of the integrator to be considerably longer than the period forone sweep during the search mode. If V changes polarity, the slope ofthe output voltage will also undergo a change of polarity, for example,from rising to falling. The slope attitude of the output will beopposite to the polarity of the input voltage due to the minus sign inthe above equation. The output of integrator 26 is applied to the tuningcircuit of local oscillator ll (FIG. 1) to effeet a change in oscillatorfrequency which is typically proportional to the output voltage ofintegrator 26.

A search voltage supply 27 provides a negative constant voltage input tointegrator 26 which generates therefrom a ris ing-voltage search ramp. Afiyback circuit 28 receives the output of integrator 26, detects anupper voltage threshold in the integrator search ramp and rapidly forcesthe integrator output voltage to a lower threshold so that anothersearch ramp can be generated. Accordingly, local oscillator 11repeatedly transverses a prescribed bandwidth of frequenciescorresponding to the integrator output voltage range.

A limit detector 29 in flyback circuit 28 momentarily interrupts voltagesupply 27 and triggers a flyback positive voltage supply 31. In order toquickly decrease the level of the output voltage of integrator 26, thevoltage provided by flyback supply 31 is a large positive voltage,typically times the numerical value of the negative search voltage.

Referring to FIG. 3, a pair of blocking oscillators 32 and 33 in limitdetector 29 fire respectively when an upper or lower voltage thresholdis exceeded by the output of integrator 26. A flip-flop 34 having setand reset inputs and two corresponding outputs provides gating signalsfor search supply 27 and flyback supply 31. When upper blockingoscillator 32 fires, flip-flop 34 is set and fiyback supply 31 isactivated supplying a large positive voltage to integrator 26. At thesame time the signal on the lead to search supply 27 inhibits the searchvoltage output to integrator 26. The integrator output voltage quicklyfalls to the level where lower blocking oscillator 33 is triggeredresetting flip-flop 34. The inhibit signal is removed from supply 27 andflyback supply 31 is inhibited until the search ramp is regenerated tothe upper threshold. A positive video pulse passing from discriminator16 via amplifier 17 cuts ofi' search voltage supply 27 and activates acorrection voltage control 41.

Referring now to FIG. 4, amplified positive and negative video voltageis passed respectively via diodes 42 and 43 to the set and reset inputterminals of a conventional flip-flop 44 in correction voltage control41. The polarity at the input terminals of flip-flop 44 is the same dueto the inclusion of an inverter 45 between diode 42 and the set input offlip-flop 44. ln the lock mode during normal excursion of the IFfrequency about the discriminator center frequency, the output offlipflop 44 will be switched successively from a high level to a lowlevel. Settable positive and negative voltage supplies 47 and 48 aregated on respectively by the high and low levels of the output offlip-flop 44. The local oscillator frequency correction rate in eitherdirection is determined by adjusting the levels of supplies 4'7 and 48.

In operation the local oscillator frequency varies between a prescribedminimum and maximum frequency as shown in FIG. 5 where the search modeof operation is depicted. The rising portion of the frequency curveassociated with local oscillator 11 (L0) represents the search rampwhile the steeper falling portion represents the effect of the flybackvoltage. The oscillator frequency is approximately proportional to theoutput voltage level A of integrator 26. Line B of FIG. 5 represents thechanging input voltage to integrator 26. The integrator output A risesunder the influence of the negative search voltage of line G. When theupper limit is detected by limit detector 29, blocking oscillator 32provides a pulse output in line C which sets flip-flop 34 causing outputE to rise which in turn activates the positive flyback voltage supplyoutput l-l. Flip-flop output F simultaneously drops to the lower levelinhibiting the negative search voltage supply output G which returns tozero. Integator output A quickly falls as backward integration of thelarge positive voltage occurs until the lower limit is detected causingblocking oscillator 33 to provide a pulse output D which resetsflip-flop 34. Flip-flop outputs E and F are thus switched back to theirnormal state wherein the search voltage supply is enabled and theflyback voltage supply is inhibited. Successive voltage ramps aregenerated to provide a swept frequency band. Prior to lock the mode theIF frequency lies outside of the discriminator bandwidth and noefi'ective video output is present.

In FIG. 6 the operation is illustrated as the system goes from search tolock mode upon detection of the desired IF. At r, down mixer 10 receivesa pulsed radar signal having a constant P.R.F. and a carrier frequencyRF The frequency of local oscillator 11 is assumed to be traversing theselected bandwidth as represented by the integrator output A. When theIF or difference frequency enters the discriminator bandwidth, negativepulses occur. The first negative pulse having a magnitude above thelower threshold does not, however, place the system in the lock mode.Instead the search ramp of output A continues, and the IF passes throughthe discriminator center frequency until, at time t, a positive videopulse, above threshold, signals the end of the search mode and thebeginning of the lock mode. The positive video pulse at r, inhibits thesearch voltage supply and allows the correction voltages to be appliedto integrator 26. Lines I and .I in FIG. 6 represent respectively theset and reset inputs to flip-flop 44 (FIG. 4). Since flip-flop 44 hasbeen reset at the beginning of the search mode the pulses in line I haveno effect, However, the pulse in line .I at r, representing a positive,abovethreshold video, causes flip-flop output K to go high. Negativevoltage supply 48 is gated open only during the low condition offlip-flop 44 output K. Therefore, supply 48 is switched off as shown inline N at t: On the other hand, positive voltage supply 47 is gated openin response to high condition of output K, output P providing positivevoltage to integrator 26. The composite change in integrator inputvoltage is shown in line B. The positive correction voltage, like thenegative correction voltage, is typically five times the magnitude ofthe search voltage. Thus in lock mode the rate of fall in the integratoroutput A is somewhat steeper than the rising search ramp. As theintegrator output A falls below V corresponding to the desired localoscillator frequency f}, the discriminator output V changes accordingly.In FIG. 6 the slope of the correction voltages has been adjusted inaccordance with the pulse repetition frequency so that correction takesplace on a pulse which falls exactly at the threshold voltage of thevideo output. Assuming two pulses occur before the IF frequency producesthe proper video output, the first pulse will occur at a time when theIF or difference frequency is equal to the discriminator centerfrequency. At t, the local oscillator frequency has decreased far enoughbelow its desired frequency )1, so that pulsed IF produces a negative,above-threshold video pulse. This pulse in line I resets flip-flop 44and output K falls to the low condition in which positive voltage supply47 is gated off and supply 48 is activated providing negative voltage tointegrator 26 as shown in line B. Integration of the negative voltageproduces a linear frequency correcting output ramp in line A. Time I,like 1, marks the appearance of a positive video pulse which setsflip-flop 44 causing output K to rise again and negative voltage to besupplied to integrator 26. The local oscillator frequency follows atriangle waveform centered approximately on the desired frequency j},which, when mixed with the memorized IF frequency, produces the desiredRF replica output. The excursions of the local oscillator frequencyabout )1, may represent negligible frequency error if the upper andlower thresholds of the discriminator video output are appropriatelyreduced.

The system 's ability to cope with noise spikes while in the lock modeis illustrated at 2, (FIG. 6). The spike appearing with the RF signal isassumed to include frequencies which, when combined with the localoscillator frequency, produce a positive video output from thediscriminator. The worst possible time for a spike to occur would bejust after and in the opposite direction of a correction pulse. Forexample, it is assumed that at r, a negative video pulse occurredcausing negative voltage to be supplied to integrator 26 which began togenerate a rising correction ramp in line A. The occurrence of a noisespike in the wrong direction toggles flip-flop output K causing thefalling output voltage of integrator 26 in line A to be resumed. Athowever, a negative video pulse corrects the voltage ramp causing thenegative voltage supply to be again switched on to increase the level ofoutput A. In the absence of noise spikes, output A underwent excursionof :tAV on either side of the desired voltage V o Because of the noisespike at I, an additional -AV deviation occurred producing a totaldeviation of 2AV. Thus if a noise spike of the correct frequency occursat just the wrong time, the worst effect on the system will be to doublemomentarily the deviation of output A. It is conceivable that such noisespikes could occur in succession and decrease the local oscillatorfrequency to such an extent that the IF frequency would be driven out ofthe discriminator bandwidth destroying the RF lock. Nevertheless, sincenoise is usually random in frequency and time, a low probability existsfor the successive occurrence of the necessary spikes. It should benoted that if the noise spike at I, had been of correct frequency toproduce a negative video output, there would have been no effect onoutput A. Those skilled in the art will recognize that there arenumerous other instances where isolated noise spikes will havepractically no effect on the lock mode.

Referring again to FIG. 6, the next occurrence of a negative video pulseat t, has no effect on the rising voltage of output A since flip-flop44, output K, has already been set at 1,. Output A continues to riseuntil I, where an RF pulse coincides with a local oscillator frequencysufficient to produce a positive video output. If, at I, when the RFpulse occurred, output A had not risen far enough, the video outputmight fail to reach threshold causing output A to continue to rise untilthe next RF pulse was met at r,,, In this event the deviation of outputA above V would also be approximately ZAV. In FIG. 6, however, it isassumed that a positive, above-threshold video pulse occurs at I.reversing the direction of correction. The local oscillator frequencywill remain locked on the desired frequency until reset or until theRF... radar pulses disappear. If the RF carrier frequency changes, thedesired V level in integrator output A would change to a correspondingnew level. The system would remain in the lock condition and track thechanging RF input signal.

The RF output of the system of FIG. I is essentially the sum of the IFor difference frequency and the RF of local oscillator 11. The output ofoscillator 11 is CW; therefore, if the IF is also CW, the system outputwill be 2 CW RF signal. If the IF input to mixer 22 is from circulatingmemory 2] (FIG. I), the system output is an RF pulse train. That is, theCW local oscillator output will be modulated by the pulse envelope frommemory 21. The resultant RF output from up mixer 22 will be a series ofpulses at the RF carrier frequency, but with a pulse width equal to thatof the pulses retained by memory 21.

The IF input to mixer 22 does not necessarily have to be from memory 2].The memory feature of the system of FIG. I is useful in cases where theRF carrier frequency is varying and tracking is necesary or where theP.R.F. is irregular. It is possible, however, to mix the localoscillator frequency with an IF signal produced by a fixed frequency IFoscillator producing a CW output. The oscillator frequency would beadjusted in accordance with the system IF frequency output from downmixer 10 or permanently set at the discriminator center frequency. Italso may be desirable in some cases to delete circulating memory 2! andprovide direct input from divider 14 to mixer 22. Such connection wouldbe permimible in cases where the RF carrier frequency remainedrelatively constant.

Those skilled in the art will recognize mat the discriminator bandwidth,threshold values and correction rates associated with voltage supplies47 and 48 can be optimized with respect to the expected P.R.F. or datarate and frequency stability of the RF signal. The optimum correctionrate is one that provides a frequency change at the voltage conuolledoscillator that is fast enough to follow frequency changes of the inputsignal, but slow enough to prevent the local oscillator from forcing theIF frequency out of the discriminator bandwidth before receiving asubsequent RF pulse.

Numerous advantages are achieved by the present system. A controlledrate of frequency correction in two directions is permitted. Thecorrection rate has been made independent of the magnitude of thefrequency error. A single pulse is sufficient to place the system in thelock mode. However, subsequent noise spikes have little effect on theoscillator frequency. in the typical situation the worst effect of anoise spike would be to double the frequency error momentarily. Byallowing a controlled correction rate in both directions, the trackingcapability of the present system can be optimized for a given data rate.Moreover it is possible to search at one rate, correct downwardly atanother rate and correct upwardly at still another rate, thus providingadded flexibility over prior art search lock devices. Since thefrequency correction is nonproportional to the magnitude of the error,and interpulse disturbance can only change the direction, but not themagnitude, of the AFC correction. Thus, the system is relativelyinvulnerable to break-locks due to interpulse noise. The system willremain locked in a moderately noisy environment if enough RF, pulses areavailable to keep the input signal in the discriminator bandwidth.

When the system is used in conjunction with the IF circulating orring-around memory, the RF output signal varies in frequency from thepreceding RF pulse only by the magnitude of the AFC oscillator frequencychange which is controlled by the AFC correction rate. Thus a highfrequency RF output, which differs from the RF input in only hundreds ofcycles depending on the correction rate setting, may be obtained a fewmicroseconds after the input pulse was received. A controlled correctionrate AFC system according to the invention will operate satisfactorilywith a memory system and is capable of accurate frequency reproductioneven with received signal-to-noise ratios as low as 3 db. A proportionalAFC system would correct on each noise spike, ordinarily breaking AFClock with this high a noise ratio. The prior art bang-bang AFC systemachieves a high degree of design simplicity by using the same rate ofcorrection for search and lock modes at the sacrifice of noise immunity.On the other hand, the present invention, by employing a commonintegrator having switchable constant inputs achieves both designsimplicity and noise immunity.

It will be understood that various changes in the details, materials,steps and arrangements of parts, which have been herein described andillustrated in order to explain the nature of the invention, may be madeby those skilled in the art within the principle and scope of theinvention as expressed in the appended claims.

What is claimed is:

l. A search-lock system for detecting and monitoring a discrete RF inputsignal against a background of random noise, comprising:

a voltage controlled oscillator;

first mixer means having inputs adapted to receive an RF signal andconnected to receive a portion of the oscillator output for providing anIF difi'erence signal;

discriminator means having an input operatively connected to said firstmixer means and receiving the IF signal for providing first or secondoutput signals when the IF signal is respectively within a firstbandwidth above a predetermined reference frequency or within a secondbandwidth below the predetermined reference frequency;

integrator means having an output connected to the oscillator input toprovide a control signal thereto;

a search generator having outputs selectively applying a first highsignal or first low signal to the integrator input for producing a firststep function at said integrator input, said search generator having aninput connected to the discriminator means output inhibiting the searchgenerator outputs in response to said discriminator means first outputsignal; and

a correction generator connected between the discriminator means outputand the integrator input applying a second high or a second low signalto the integrator input in response to said discriminator means first orsecond output signals respectively for producing a second step functionat the integrator input;

whereby the oscillator output is maintained at a predetermined frequencylevel relative to the RF signal.

2. A search-lock system according to claim 1 further comprising:

second mixer means having inputs operatively connected to receive the IFdifference signal and the oscillator output for combining the inputsthereof to produce a sum signal corresponding to the RF signal.

3. A search-lock system according to claim 2 further comprising:

mearm connected between the first mixer means output and the secondmixer means 1F input for storing the [F difference signal and producinga delayed replica output thereof to said second mixer means.

4. A search-lock system according to claim 3 wherein:

said storing means comprises an IF circulating memory.

5. A search-lock system for detecting and duplicating a discrete RFinput signal against a background of random noise, comprising:

a voltage controlled oscillator;

first mixer means having inputs adapted to receive an RF signal andconnected to receive a portion of the oscillator output for providing an[F difl'erence signal; discriminator means having an input coupled tothe first mixer means output and operatively receiving the IF signal forproducing a video output indicating that the IF signal frequency iswithin prescribed limits above or below a predetermined frequency;automatic frequency control means connected between the oscillator inputand the discriminator means output for applying a search signal to saidoscillator to cause the oscillator output frequency to traverse aprescribed bandwidth, and responsive to said discriminator means outputfor inhibiting the search signal to apply predetermined correctionsignals to said oscillator; memory means having an input connected toreceive the [F signal and producing a delayed replica thereof; and

second mixer means having inputs operatively connected to the memorymeans output and the oscillator output for combining the inputs thereofto produce a sum signal corresponding to the RF signal.

6. A search-lock system according to claim 5 wherein:

said discriminator means video output includes a first or a secondsignal when the [F signal frequency is respectively within a firstbandwidth above the reference frequency or within a second bandwidthbelow the reference frequency, the first and second bandwidths beingseparated by a predetermined frequency gap centered on the referencefrequency, and

said automatic frequency control means comprises integrator means havingan output connected to the oscillator input, first and second voltagesupply means for applying respectively a first high and a first lowsignal to the integrator input, limit detector means connected to theintegrator output for activating the first or second supply meansrespectively in response to a first or second predetermined level of theintegrator output, third and fourth voltage supply means for applyingrespectively second high and second low signals to the integrator input,meam for inhibiting the first high and low signals in response to saiddiscriminator means first signal, and switch means for activating thethird or the fourth supply means in response to said discriminator firstor second signal.

7. A search-lock system according to claim 6 wherein:

said memory means comprises an IF circulating memory.

8. A search-lock system for detecting and duplicating a discrete RFinput signal against a background of random noise, comprising:

search signal generating means;

control means connected to said generating means for causing thefrequency of the search signal to traverse a prescribed bandwidth;

first means connected to said generating means for combining an inputsignal with the search signal to produce a difference signal;

means connected to said first combining means for storing the differencesignal;

means connected to said first combining means for comparing thedifference signal frequency with a predetermined reference frequency;

means connected to said comparing means for generating first or seconderror signals indicating respectively that the difference signalfrequency is within prescribed limits above or below the predeterminedreference frequency;

means connected to said control means inhibiting the traverse of thesearch signal frequency in response to the first error signal;

means connected to said generating means for correcting the searchsignal frequency in one direction in response to the first error signalat a rate independent of the magnitude of either error signal;

means connected to said generating means for correcting the searchsignal frequency in the opposite direction in response to the seconderror signal at a rate independent of the magnitude of either errorsignal; and

second meam connected to said storing means and said generating meansfor combining the search signal with the stored difference signal toproduce a sum signal which is a replica of the input signal.

i i i i

1. A search-lock system for detecting and monitoring a discrete RF inputsignal against a background of random noise, comprising: a voltagecontrolled oscillator; first mixer means having inputs adapted toreceive an RF signal and connected to receive a portion of theoscillator output for providing an IF difference signal; discriminatormeans having an input operatively connected to said first mixer meansand receiving the IF signal for providing first or second output signalswhen the IF signal is respectively within a first bandwidth above apredetermined reference frequency or within a second bandwidth below thepredetermined reference frequency; integrator means having an outputconnected to the oscillator input to provide a control signal thereto; asearch generator having outputs selectively applying a first high signalor first low signal to the integrator input for producing a first stepfunction at said integrator input, said search generator having an inputconnected to the discriminator means output inhibiting the searchgenerator outputs in response to said discriminator means first outputsignal; and a correction generator connected between the discriminatormeans output and the integrator input applying a second high or a secondlow signal to the integrator input in response to said discriminatormeans first or second output signals respectively for producing a secondstep function at the integrator input; whereby the oscillator output ismaintained at a predetermined frequency level relative to the RF signal.2. A search-lock system according to claim 1 further comprising: secondmixer means having inputs operatively connected to receive the IFdifference signal and the oscillator output for combining the inputsthereof to produce a sum signal corresponding to the RF signal.
 3. Asearch-lock system according to claim 2 further comprising: meansconnected between the first mixer means output and the second mixermeans IF input for storing the IF difference signal and producing adelayed replica output thereof to said second mixer means.
 4. Asearch-lock system according to claim 3 wherein: said storing meanscomprises an IF circulating memory.
 5. A search-lock system fordetecting and duplicating a discrete RF input signal against abackground of random noise, comprising: a voltage controlled oscillator;first mixer means having inputs adapted to receive an RF signal andconnected to receive a portion of the oscillator output for providing anIF difference signal; discriminator means having an input coupled to thefirst mixer means output and operatively receiving the IF signal forproducing a video output indicating that the IF signal frequency iswithin prescribed limits above or below a predetermined frequency;automatic frequency control means connected between the oscillator inputand the discriminator means output for applying a search signal to saidoscillator to cause the oscillator output frequency to traverse aprescribed bandwidth, and responsive to said discriminator means outputfor inhibiting the search signal to apply predetermined correctionsignals to said oscillator; memory means having an input connected toreceive the IF signal and producing a delayed replica thereof; andsecond mixer means having inputs operatively connected to the memorymeans output and the oscillator output for combining the inputs thereofto produce a sum signal corresponding to the RF signal.
 6. A search-locksystem according to claim 5 wherein: said discriminator means videooutput includes a first or a second signal when the IF signal frequencyis respectively within a first bandwidth above the reference frequencyor within a second bandwidth below the reference frequency, the firstand second bandwidths being separated by a predetermined frequency gapcentered on the reference frequency; and said automatic frequencycontrol means comprises integrator means having an output connected tothe oscillator input, first and second voltage supply means for applyingrespectively a first high and a first low signal to the integratorinput, limit detector means connected to the integrator output foractivating the first or second supply means respectively in response toa first or second predetermined level of the integrator output, thirdand fourth voltage supply means for applying respectively second highand second low signals to the integrator input, means for inhibiting thefirst high and low signals in response to said discriminator means firstsignal, and switch means for activating the third or the fourth supplymeans in response to said discriminator first or second signal.
 7. Asearch-lock system according to claim 6 wherein: said memory meanscomprises an IF circulating memory.
 8. A search-lock system fordetecting and duplicating a discrete RF input signal against abackground of random noise, comprising: search signal generating means;control means connected to said generating means for causing thefrequency of the search signal to traverse a prescribed bandwidth; firstmeans connected to said generating means for combining an input signalwith the search signal to produce a difference signal; means connectedto said first combining means for storing the difference signal; meansconnected to said first combining means for comparing the differencesignal frequency with a predetermined reference frequency; meansconnected to said comparing means for generating first or second errorsignals Indicating respectively that the difference signal frequency iswithin prescribed limits above or below the predetermined referencefrequency; means connected to said control means inhibiting the traverseof the search signal frequency in response to the first error signal;means connected to said generating means for correcting the searchsignal frequency in one direction in response to the first error signalat a rate independent of the magnitude of either error signal; meansconnected to said generating means for correcting the search signalfrequency in the opposite direction in response to the second errorsignal at a rate independent of the magnitude of either error signal;and second means connected to said storing means and said generatingmeans for combining the search signal with the stored difference signalto produce a sum signal which is a replica of the input signal.